Television receivers which feature picture-in-picture processing are known. In such receivers an inset or "small" picture to be displayed within an area of a "main" or "large" picture is subjected to vertical and horizontal compression by means of selective storage and retrieval from a memory and the compressed picture video signal is inserted within an area of the main picture video signal by means of a multiplex switch that is controlled by timing signals provided by the picture in picture compression processor. Examples of picture-in-picture compression processors are described, for example, by D. L. McNeely and R. T. Fling in U.S. Pat. No. 4,890,162 and by E. D. Romesburg in U.S. Pat. No. 4,768,083, those patents incorporated herein by reference.
It has been suggested in the article "PIX-IN-PIX DIGITAL DECODING/ENCODING USING ONLY ONE CLOCK," Rumreich, IEEE Transactions on Consumer Electronics, Vol. 37, No. 3, August 1991, pp. 210-212 to create a single integrated circuit (IC) to receive two composite video inputs and to provide an overlaid composite video output. In that article, it is described that all video decoding and encoding is performed in an IC using digital signal processing and a single clock. In the above-named article to Rumreich, the small picture Y/R-Y/B-Y data is multiplexed and stored in an 8K.times.8 SRAM located external to the IC.
An IC has been developed which includes a line comb filter for the main picture, as well as video processing circuitry for the small or sub-picture, and including a small-picture field memory on chip shares the IC with all the other active circuitry. A single clock is used by all circuitry on the IC. Some of the circuitry on the IC is analog, i.e. analog-to-digital converters, digital-to-analog converters, video switches and buffers. In the processing of a video signal to become a small picture, the signal is decoded, anti-alias lowpass filtered, subsampled and written into a small-picture field memory. The memory writing operation is a relatively high-powered operation and can generate spurious interference with other circuits on the chip. This may result in interference which appears as obvious vertical stripes in the large picture, which is processed through the line comb filter circuit of the IC. This interference also is present in the small picture by being coupled into the small picture digital-to-analog converter, again producing vertical stripes.
Additionally, although this spurious interference has been found to occur in a picture-in-picture type system, it is not limited to such a system. It is believed that the occurrence of such a vertical stripe interference pattern may occur in any video signal processed using analog circuitry (i.e. a D/A converter, etc.) to process video during repetitive high speed digital memory write operations.
What is needed is a means for reducing the interference visibility caused by spurious interference throughout the analog circuitry during repetitive memory write operations.